Title: Simulation of Hardware Dynamic Scheduling on the DLX Architecture
Author: Azer Bestavros and Yueh-Lin Liu
Date: June 6, 1995

Abstract:
We describe our extention of the existing DLX simulator (DLXsim),
available from the University of California at Berkeley, which allows
the simulation of two hardware dynamic scheduling techniques. There
are two DLXsim-like interactive simulators developed as part of this
project. DLXscore simulates the operation of a DLX architecture
equipped with scoreboarding hardware. DLXscore provides the status of
instructions, scoreboard tables, and statistics. DLXtomasulo simulates
the operation of a DLX architecture equipped with a hardware
implementation of Tomasulo's algorithm. DLXtomasulo provides the
status of instructions, reservation stations, and statistics. Both
programs allow the user to configure the number of functional units
and the latency of floating point operations.