Computer Science Department
College of Arts and Sciences
As part of the ALU of a special purpose processor, you are asked to build a special 8-bit register with the following operation specification.
---------------------------------------------------------------------- | Function Code | Action taken at the next clock cycle | ---------------------------------------------------------------------- | 0 0 0 | Do not change the contents of the register | | 0 0 1 | Compute the 1's complement of the register | | 0 1 0 | Clear all bits of the register | | 0 1 1 | Swap the high-order 4 bits with the low-order 4 bits | | 1 0 0 | Do a left circular shift of the register | | 1 0 1 | Do a right circular shift of the register | | 1 1 0 | Load all bits of the register from input in parallel | | 1 1 1 | Set all the bits of the register (to 1) | ----------------------------------------------------------------------Show the design of this register, assuming the availability of D flip-flops, and basic building blocks (e.g. gates, multiplexers, etc.)
You are given a bunch of 4-to-1 1-bit line multiplexers with an enable input. Show how you could use these to build a 16-to-1 4-bit line multiplexer.
A 38-bit floating-point binary number has 9 bits for the exponent, 28 bits for the mantissa, and 1 bit for the sign (of the mantissa). The exponent is represented as an integer equal to the value of the exponent plus 256. In other words, an exponent of +5 would be represented by the value 261, whereas an exponent of -5 would be represented by the value 251. The mantissa is normalized.
Maintainer: Azer Bestavros Created on: 1996.09.21 Updated on: 1996.09.02