Computer Science Department
College of Arts and Sciences

Computer Architecture
CS-450 / Fall 1996

Homework Assignment #5
(Due Date: 11/14/1996)

The Data Path shown in figure 1 is that of a simplified MIPS design. The processor uses 3 buses: S1, S2, and Dest. The fundamental operation of the datapath could be described in the following 5 execution cycles (stages):

Figure 1: The Datapath of the DLX architecture (click here for a larger figure)

The register file has 32 General Purpose Registers and has two output ports. This means that 2 of its registers can be fetched in one clock cycle into registers A and B. The register file is designed such that R0 has a value that is always 0. The control lines feeding the Register File allow any two of the 32 registers to be read and deposited in registers A and B in one clock cycle. In addition the register file is allowed to store the value of register C in any one of the 32 registers.

Each one of the registers in the datapath is supplied with enough control lines to enable its value to be deposited or withheld from each one of the buses it is connected to. Also, each register is supplied with a control line that allows it to ``load'' its input.

The ALU carries many different operations (you are free to pick your own, but make sure that at least the usual Arithmetic and Logical Operations are included!)

The CPU is connected to two separate memory systems: one for code (instructions) and one for data. You can assume that all memory operations complete in one clock cycle.

The machine is designed as a 32-bit machine. All data registers as well as all of the ALU datapaths are 32 bits long. The data and code memories of the machine are both 32-bit byte-addressable. This means that any memory load (store) brings in (out) 32-bit words, which could start at any byte address. Both memories can be as large as 2^26 = 64 MegaBytes. Thus, all address registers (i.e. PC and IAR) are 26 bits wide.

The ISA of this machine is that of a typical Load/Store architecture. There is only one addressing mode for this machine (typical of many RISC architectures), namely displacement addressing. In particular, the effective address of any memory access is computed by adding the contents of a register to an immediate value (provided in the instruction).

There are three types of instructions: R-type instructions, I-type instructions, and J-type instructions. The formats of these three types of instructions is shown below:

      6          5         5                        11
|  Opcode   |   rs1   |   rs2   |   rd    |        func         |

                       R-type (Register-type)

      6          5         5                   16
|  Opcode   |   rs1   |   rd    |           Immediate           |

                       I-type (Immediate-type)

      6                           26 
|  Opcode   |            Offset added to PC                     |

                         J-type (Jump-type)

The R-type instructions are used to operate on the two source registers specified by the rs1 and rs2 fields, storing the result in a third register specified by the rd field. The func field of an R-type instruction specifies an extension to the opcode field. For example, a typical ALU operation (say ADD signed) will look like:
ADD R7, R5, R6   ==>    | 010010 | 00101 | 00110 | 00111 | 00001110110 |
                          opcode   rs1=R5  rs2=R6  rd=R7      func

The I-type instructions are used to operate on one source and on one immediate data item. They are typically used for load/store operations. For example,
LW R16, R5(100)   ==>   | 111010 | 00101 | 10000 | 0000000001100100 |
                          opcode   rs1=R5 rs2=R16   Immediate=100

The J-type instructions are primarily used for unconditional jumps to addresses relative to the PC, namely PC + 26-bit offset (specified in the instruction). For example, a typical Jump instruction will llook like:
Jump 228          ==>   | 011011 | 00000000000000000011100100 |
                          opcode           Offset=228

The instructions of the machine described above can be classified into the following categories:

Answer the following questions

Maintainer: Azer Bestavros Created on: 1996.11.02 Updated on: 1996.11.02
Copyright © 1996. All rights reserved.