Scoreboarding Problem 1

This shows the basic structure of a DLX machine with a scoreboard.
Q: A shortcoming of the scoreboard approach occurs when multiple functional units that share input buses are waiting for a single result. The units cannot start simultaneously, but must serilaize(look carefully at above diagram). This is not true in Tomasulo's algorithm. Give a code sequence that uses no more than 10 instructions and show the problem. Assume the following latencies in clock cycles:

FP divide 40
FP multiply 10
FP add 2

Indicate where the Tomasulo approach can continue, but the scoreboard approach must stall.

The following are the default values of DLXscore:

Scoreboarding Hardware Configuration
 1 integer_unit,       latency =  1 cycles
 3 add/subtract units, latency =  2 cycles
 1 divide units,       latency = 40 cycles
 2 multiply units,     latency = 10 cycles

Sample solution of problem 1

This page is created by Yueh-Lin Liu(yueh@cs.bu.edu) as a part of Master project under the supervision of Prof. Azer Bestavros(best@cs.bu.edu)

Last updated: 1995.5.15